As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop testplan, testbench and testcases to verify mixed signal (digital and analog) designs.
- Generates verification specifications.
- Determines test bench design and test cases.
- Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
- Generates documentation for test plans, verification environments, and usage.
- Participate in evaluation and troubleshooting of digital and mixed signal designs.
- Candidate should have a strong desire to learn and explore new technologies.
- Demonstrates good communication skills in English.
- Demonstrates good analysis and problem-solving skills.
- Prior knowledge CAD tool for development.
- Knowledge of Verilog and SystemVerilog.
- Experience with scripting languages
- Knowledge of high speed interface protocols such as HBM, DDR, DFI is a plus.
- Understanding of verification methodology such as UVM is a plus.