Descrição
Description:
- Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- Timing, physical and electrical verification, and driving the signoff closure for the partitions.
- Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Requirement
- Bachelor’s degree or higher in Electrical and Electronics Engineering.
- At least have 4 years working experience
- Knowledgeable in partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Strong knowledge of physical design construction and analysis flows and methodology.
- Shown ability to adhere to stringent schedule and die size requirements.
- Strong communication skills.
- Experienced with industry standard tools, understanding their capabilities and underlying algorithms.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
- Proficient in scripting languages (i.e. Perl, Python, TCL).
- Demonstrate knowledge of basic SoC architecture and HDL languages to collaborate with logic design teams to drive optimizations in power, performance, and area.
- Experience in IP-level planning (block tiling, feedthrough planning, pin assignment).
- Solid understanding of Extraction and STA methodology and tools.
Salary: From $4,500.00 per month
Schedule:
- Monday to Friday
Ability to Commute:
- Singapore 469032 (required)
Ability to Relocate:
- Singapore 469032: Relocate before starting work (required)