Descrição
Job Details:
- The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations for the cutting-edge DDRPHY IPs.
- You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools for Lint, CDC, RDC, Voltage domain crossings, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to contribute to automating various Front End Tool, Flows and Methodologies and innovating the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams.
Objectives of the position
- Own and deliver the logic design of Mixed Signal IPs.
- Continuously drive improvement in the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements.
- Drive area/power of IPs and come up with improvements on IP Area/Power metrics.
- Critical Decision making on technical issues.
Job Type:Experienced Hire
Shift:Shift 1 (India)
Primary Location:India, Bangalore
Additional Locations:
Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust:N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.